Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices

This paper evaluates Differentiable Logic Gate Networks (Diff-Logic) for low-latency EEG classification on edge devices. The models are compiled into Boolean circuits and executed with bitwise CPU operations, avoiding conventional floating-point inference. Across four EEG datasets, two tasks, and matched parameter tiers from 50k to 500k, Diff-Logic reached 80.2% Macro F1 for binary dementia detection, 6.8 percentage points above the MLP baseline. For three-class emotion recognition, MLPs performed better, but Diff-Logic delivered 2.3x lower latency and a 14x smaller model on a single-core, 7W Jetson Orin Nano CPU. Its inference time stayed nearly constant as model scale increased tenfold.