Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

This paper presents an open-source framework for complete on-device neural-network training on resource-constrained RISC-V single-core systems. It uses the standard Zfh scalar Float16 and Zvfh vector Float16 extensions, reporting roughly 50% lower memory footprint than Float32 with minimal model-performance degradation. The framework builds on AIfES and supports transfer learning, fine-tuning, and layer freezing. For an RV64GC superscalar out-of-order FPGA softcore at 175 MHz, adding Zfh reportedly increases resource usage by only 1.15% in LUT6 and 0.05% in flip-flops. The paper also outlines a Zvfh implementation.